1. Field of the Invention
The present invention is related to processor verification and simulation software, as well as to processor hardware implementations that provide support for product verification and test.
2. Description of Related Art
Modern processors and processing systems increasingly incorporate high degrees of parallelism and on-the-fly optimization (e.g., execution re-ordering) that cause completion timing of individual program instructions (usually determined in numbers of processor clock cycles) to vary significantly. Further, a number of resources, e.g., internal registers, caches and queues are typically provided in sufficient quantity to avoid frequent full allocation of resources.
Verification of processor and processing systems includes software simulation and hardware test. Simulation of processor operation is performed during design of a processor and also during design step iterations after prototype and/or production parts have been manufactured. Simulation is typically carried out using workstation computer systems running high-level software that stimulates and simulates a circuit model of the processor, which is typically a Very High-level Description Language (VHDL) circuit model. Hardware test is performed on both prototype devices and production devices, with more in-depth (lengthier) test sequences reserved for the pre-production verification environment. The purpose of verification, both in simulation and hardware test, is to ensure that increasingly complex processor and processing system designs operate as intended.
However, effective simulation of very complex designs requires extremely lengthy and complex test and simulation sequences, since ideally all states of the logical circuit comprising the process should be verified. In actuality, all states may not be verifiable, and the above-mentioned parallelism and on-the-fly optimization of modern processors complicates the simulation and testing process, as it may be difficult to cause a processor or processing system to reach the limits of resource usage and otherwise reach similar states that are only entered under unusual operating conditions. In other words, it may not be possible to exercise such an optimizing processor in order to reach the resource limits and test logic that handles resource over-demand and other conditions that occur during high resource usage, unless artificially-induced high-resource-demand conditions can be introduced.
In the past, simulation of the above-described high-resource-demand conditions has been attempted by a test program instructions including program instructions that require many cycles to complete, such as load instructions that miss the data cache, floating point divides or square root computation, and sequences of instructions having interdependencies. Execution of such instructions are simulated in order to tie up resources for as long as possible, but fall short of the desired degree of control that is necessary to detect and analyze a particular defect and control resource usage, in particular to simulate processing scenarios that have high levels of resource usage. As described above with respect to simulation, testing of actual devices could be further facilitated by providing mechanisms within a processor that facilitate exercising resources in order to enter states that are difficult to reach during normal test program execution.
Therefore, it would be desirable to provide a method and apparatus that provide control of program instruction completion time both in simulation and test verification environments.